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Course Outline and Syllabus Flipbook PDF
Course Outline and Syllabus
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Advanced Real Number Modeling with SystemVerilog Course Navigation The course consists of video segments of approximately 30 minutes each, with associated exercises. The topics covered in each session are listed below. If there is an exercise associated with a particular video session, a link to a guiding document will appear in the video player frame below the video. The files database needed to complete the exercises, which also includes example files referred to in the videos, should be downloaded and installed on your local linux system where the needed tools are installed. You only need to do this once. Look for the link to “Database Downloads” on the left. Some initial setup is required and instructions will be found in the Session 02 Exercise guide.
Course Syllabus Session 1: Introduction • • • •
Why Model? Verification Methodologies AMS or DMS? Uses and Limitations of Real Valued Modeling
Session 2: SystemVerilog Language Features • • • • •
Real variables, real ports, real nets Event and Delay Control Useful Built-in Functions Net Resolution User Defined Net Types o Exercise: Built-in Nettypes and Resolution Functions o Exercise: User Defined Nettypes with Resolution Functions
Session 3: Fundamental Behavioral Modeling Best Practices • • • • •
Verification Planning Model What is Important Properly handle all inputs and states Focus on Efficiency Helpful Simulator Options
Session 4: Circuit Types I – Filters • • • • •
Managing Input Waveforms Sampled-time Filter (IIR Approximation) Event-Driven Filter with Slew Limiting FIR Filters Test Bench Construction o Exercise: 2-pole Low-pass Filter
Session 5: Circuit Types II – Gain and Signals • • •
Programmable Gain Amplifier Voltage Controlled Oscillator Test Bench Construction o Exercise: VCO Exercise
Session 6: Circuit Types III – ADC, DAC, Signal Sources • • • •
Step Source ADC DAC Test Bench Construction o Exercise: Signed ADC and DAC
Session 7: Introduction to EEnet UDN • • • •
UDN vs ‘ordinary’ real EEnet Defined Type (UDT) res_EE Resolution Function (UDR) Simple Examples o Exercise: Review EE_pkg, use EEnets to drive any combination of V, I, and R
Session 8: Defining Interconnections Between EEnet Nodes • • • • •
Definition of an EEnet Differential Resistor Basic solution of differential element format Bounding iterations when defining cross-coupled events Use of $cds_get_external_drivers for bidirectional signal access Use of EEIO module to simplify EEnet differential element design o Exercise: EEnet Resistor Divider Network
Session 9: Modeling Capacitors and Inductors in EEnet • • • •
Modeling a Capacitor Timestep control and continuous signal assumption Defining a differential Capacitor Modeling an Inductor o Exercise: RLC Circuit o Exercise: Charge Pump Voltage Doubler
Session 10: Handling Feedback and Nonlinearities in EEnet Networks • • • •
Processing of networks of differentially-connected EEnet elements Proper iteration control procedures Special cases: resistor ring, nonlinear element, amplifier with feedback Summary of Limitations o Exercise: MOS diode characteristic
Session 11: Reconciling Real Number Models with their SPICE Counterparts • •
Introduction to State Space Modeling Example: model circuits with state elements (L, C) using finite difference equations
Session 12: Circuit Types IV •
Phase Locked Loops o Exercise: PLL - Trapezoidal Integration
Session 13: Including Efficient RF Nets • • •
Efficient Real Valued RF Including Modulation and Power Ramps Building Circuit Models with RF Responses o Exercise: Low Noise RF Amplifier
Session 14: Circuit Types V – LDO • • • • •
Block Diagram Convert to EEnet Controlling the Response Test Bench Construction Maintaining Stability
•
Modeling Startup Behavior o Exercise: LDO Simulation
Session 15: EEnet Advanced Concepts I: Generating Time-Varying Signals • • •
Modeling simple risetime effects Basic modeling of ramping signals Designing time-varying signals that can interact properly with other drivers o Exercise:
Session 16: EEnet Advanced Concepts II: Handling Switches in EEnet Systems • • • •
Simple switching operations Switching issues in capacitive or inductive networks Extensions to capacitor and inductor models for use in switched networks Summary of Available Building Blocks o Exercise: Buck converter o Exercise: Capacitor mode comparison
Session 17: Circuit Types VI – Translating from Schematics RF Mixer • •
Mixer Circuit Mixer SystemVerilog
Trans-impedance Amplifier • • •
TIA Circuit breakdown TIA Block Model TIA SystemVerilog o Exercise: TIA Continuation
Session 18: Mixing UDNs with Single-value Real Nets • • • •
Avoiding Connect Modules Built-in Connect Modules Custom Connect Modules
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Exercise: Reference Distribution Block
Session 19: Additional Concepts • • • • •
Using $table_model Integration Differentiation Sampling with Averaging Sampling with Integration o Exercise: Enhanced Integrator with Iteration Control
Session 20: Instrumenting Analog Measurements • •
Verifying Mixed Signal System Function Special Purpose Modules: Rise/Fall Time, Slew Rate, RMS, FFT o Exercise: PLL Lock Time Measurement
Session 21: Using SV Assertions for Verification • • • • • • • •
Why Use Assertions? Immediate Assertions Concurrent Assertions Assertion Sampling Mechanics Parameterized Assertions for Building Libraries Controlling Assertion Behavior Using bind to Attach Assertions Debugging Assertions o Exercise: PLL Lock with Assertions
Session 22: Applying Randomness for Mixed Signal Verification • • • • •
Uses of Randomization in Verification Including and Applying Randomness to Real Models Generating Random Real Valued Stimulus Focus on Constraints Controlling Random Number Generation with Xceligen
o
Exercise: PLL with Randomness
Session 23: Using SV Coverage Constructs • • • • • •
What is Coverage? SystemVerilog Language Constructs Coverage Location Options Coverage Sampling Enabling Coverage Viewing Coverage Results o Exercise: PLL with coverage
Session 24: Managing Varying Levels of Abstraction • • • • • •
Top-Down Design Methodology Virtuoso Hierarchy Editor Configuration SystemVerilog Configuration File List Inclusion Keeping Models in Sync with Circuits SAR ADC Example o Exercise: SAR ADC
Session 25: VerilogAMS vs SystemVerilog • •
Comparing Electrical vs Real Model Implementations Example: Reference Voltage and Current Generator o Exercise: Reference Voltage and Current Generator
Session 26: Using the Xcelium Profiler to Optimize Performance • • • •
Activate the Xcelium Profiler Reading Profiler Output Useful Profiler Options Using the Advanced Profiler with GUI o Exercise: None
Session 27: Including Power Intent with Real Number Models • • • •
Power Intent Review Power Intent in a Mixed Signal Design IEEE-1801 (UPF) Using Real Valued Supply Nets
•
Using UDN Supply Nets o Exercise: RxBB Design with Power Intent
Session 28: Mixed Signal Partitioning and Multi-Core Optimizations • • •
Multi-Snapshot Incremental Elaboration (MSIE) Process-based Save/Restart Multi-Core Simulation Options