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Lumped Approximation - University of California, Berkeley Flipbook PDF
Lumped Approximation The dimension of the physical circuit is small enough so that electromagnetic waves propagate acros
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Lumped Approximation The dimension of the physical circuit is small enough so that electromagnetic waves propagate across the circuit “almost” instantaneously.
Rule of Thumb Lumped Approximation is valid if d c i ∆t d = largest dimension of the physical circuit ∆t = smallest signal response time of interest = 1/max. frequency of interest
c = 3 × 10 m / sec 8
Example : hi-fi set max. frequency of interest = 25 Khz ∴ Lumped approximation holds if
d
1 3(10 )m / s • = 12 Km 3 25(10 ) ≈ 7.5miles 8
∴ Even if the circuit is spread across a football stadium, it satisfies the lumped approximation.
Consequences of Lumped Approximation 1. Electrical behavior does not depend on the physical size, shape, and orientation. Only the physical interconnections are relevant. Hence each device can be lumped into a point, as in classical mechanics. 2. Voltages and currents at any terminal of the physical circuit are well defined.
Basic Circuit Theory 3 Postulates : 1. Lumped Approximation 2. Kirchhoff Current Law (KCL) 3. Kirchhoff Voltage Law (KVL) Circuit Theory is applicable if, and only if, the above 3 postulates are satisfied.
Current is a “through” variable Current measured
by
is
always
inserting
an
Ammeter through 1 point of a device terminal or wire.
1. All
wires
are
Assumption 1 conducting
conductors (zero resistance).
perfect
2. All circuit interconnections are perfect.
Consequence
Two terminals joined by a wire is
wire
≡
equivalent to a single terminal. j
k
Quantum Mechanical Tunneling makes perfect contacts
Since the 2 metal prongs of an
electrical plug has a thin oxide layer
(perfect insulator) on all sides, the perfect
contact established when it is plugged into a
socket is due to a quantum-mechanical phenomenon called tunneling.
Reference Current Direction and Voltage Polarity Since the current i(t) entering an electrical terminal k and the voltage vjk(t) across a pair of terminals j and k in a typical electrical circuit can assume a positive value at one instant of time, and a negative value at another instant of time, it is necessary to assign (arbitrarily) a current reference direction for each terminal current, and an a pair of voltage polarity reference, across every pair of terminals. If the calculated current (resp., voltage) at some instant of time turns out or be a negative number, it simply means that the actual current (resp., voltage) is opposite in direction (resp., polarity) to the arbitrarily assigned reference at that instant of time.
4 possible reference assignments for a 2-terminal device j
+
j
im
+
v jk
v jk
-
-
im
k
k
j
j
-
im
-
v jk
v jk
+
+ k
im
k
Reference current direction and reference voltage polarity can be arbitrarily assigned.
2 Among many possible reference assignments v jk
+
j
-
-k
iα
iβ
+ vkl
v jl
+ l
iγ
-
v jk
+
j
-
-k
iα
iβ
vkl
v jl
iγ
+ + l
Note: When two terminals whose voltage polarity is being assigned are far apart, we often draw a doubleheaded arrow to identify the associated pair of terminals.
Associated Reference Convention Although the reference current direction and the voltage polarity can be arbitrarily assigned, for pedagogical reasons, we will agree on the following associated reference convention: i1
1
+
1
i1
i2
+
2-terminal device
+
i2
- -
n
ik
i1
in
v2
v1
-
+
1
+
v1 2
+
k
2
2
- -
3 (datum)
n+1 (datum)
3-terminal device
(n+1)-terminal device
Current is assigned entering the positively referenced non-datum terminal.
+
Voltage is an “across” variable Voltage
is
always
measured by connecting a
voltmeter across 2 device terminals or nodes.
Gustav Robert Kirchhoff (1824-1887)
Gaussian Surface Any
closed
surface
that has an inside and an outside
is
called
Gaussian surface.
a
KCL
i3 i1 i8
D3
D1
i4 i6
D2 i2
i5
i7
KCL Gaussian Surface 1
i3 i1 i8
D3
D1
i4 i6
D2 i2
i5
i7
Gaussian Surface 1: i1 − i 3 + i8 = 0
Nodes Definition Any terminal (i.e., wires) attached to a device in a circuit where 2 or more terminals are soldered together is called a node.
Remarks: 1.
We can always draw a sufficiently small sphere centered at each node of a circuit such that the sphere is pierced only by the currents entering the node.
2.
A sphere is the simplest Gaussian surface.
KCL i3 i1 i8
D3
D1
i4 i6
D2 i2
i5
i7
Applying KCL to a small Gaussian surface enclosing each node ⇒ Corollary 1 The algebraic sum of all currents leaving a node is zero.
KCL Gaussian Surface 2
i3 i1 i8
D3
D1
i4 i6
D2 i2
i5
i7
Gaussian Surface 2: i 3 + i 5 + i 7 = 0
KCL Gaussian Surface 3
i3 i1 i8
D3
i4
D1
i6
D2 i2
i5
Gaussian Surface 3:
i1 − i3 + i 4 − i 6 + i8 = 0
i7
Cut set Definition: A subset of currents ia, ib …, im from a physically connected circuit forms a cut set iff the following 2 conditions are satisfied: 1.
Cutting (say, with a plier) all “m” terminals (wires) would physically disconnect the circuit into 2 or more components.
2.
Cutting only m-1 terminals (wires) from (the subset
of
currents
would
not
physically
disconnect the circuit. Remarks: 1.
Given any cut set {ia, ib …, im }, we can always draw a Gaussian surface pierced only by {ia, ib …, im }.
2.
Once a Gaussian surface is chosen, we define the direction of each current entering the surface to be the positive orientation of the cut set.
3.
A cut set with an assumed positive orientation is said to be an oriented cut set.
KCL Positive orientation
i3 i1 i8
D3
D1
i4 i6
D2 i2
i5
i7
Gaussian Surface enclosing a cut set
{i2 , i4 , i5 , i8 }
is a cut set because
1. It cuts the circuit into 2 parts. 2. Any 3 out of 4 currents in the set will not cut the circuit.
KCL Positive orientation
i3
D3
i1 i8
D1
i4 i6
D2 i5
i2
i7
Gaussian Surface enclosing a cut set
{i2 , i3 , i4 , , i5 , i8 }
is not a cut set because
the sm aller subset {i2 , i4 , i5 , i8 }
can already cut the circuit into 2 parts.
KCL Gaussian surface defining a cut set Arbitrarily assigned positive orientation of the cut set
i3 i1 i8
D3
D1
i4 i6
D2 i2
i5
i7
Applying KCL to a Gaussian surface associated with a cut set Corollary 2
⇒
The algebraic sum of all currents in a cut set relative to its assigned positive orientation is zero.
KCL i3 i1 i8
D3
D1
i4 i6
D2 i2
i5
i7
Applying KCL to a Gaussian surface enclosing each device ⇒ −i1 + i2 = 0 i3 − i4 + i5 = 0 i6 + i7 = 0
Node-to-datum and Branch voltages In order for work to occur, the test charge has to be moved over some distance. So voltage always involves two positions, a starting point and an ending point. To avoid ambiguity, we must always specify a voltage across 2 points in a circuit, called nodes, unless one of the 2 nodes is the circuit ground node, called the datum node. Such a voltage is called a node-to-datum voltage, and will always be denoted by ej. Any other voltage is called a branch voltage, and will be denoted by vj.
Kirchhoff Voltage Law
KVL node j
v jk
+
node k
+
+
ej
ek -
Connected Electrical circuit
Datum node
The voltage vjk(t) between any 2 nodes and
k
j
is equal to the difference between the 2
associated node-to-datum voltages ej and ek, for all times t.
v jk (t ) = e j (t ) − ek (t )
KVL Corollary 1 (around closed node sequences)
Algebraic sum of all voltages around any closed node
sequence
in
any
connected circuit is equal to
zero at all times t.
+ v1 D1
v -3+ D3
e1
-
D2
+ v4
2
D4
e2
-
-vD +
e3 +
5
e4
3
v3−5 6
7
D8
D6
-v
+ v8
-
5
KVL ⇒ v = e − e 1 1 3
+
v7
-
+
4
5
D
1
+ v2
e5 = 0
v2 = e2 − e4
v5 = e4 − e3 v6 = e5 − e1 = −e1
v3 = e2 − e1
v7 = e4 − e5 = e4
v4 = e2 − e3
v8 = e2 − e5 = e2
Consider Loop formed by closed node sequence 1
2
5
1
:
−v3 + v8 + v6 = −(e2 − e1 ) + (e2 − e5 ) + (e5 − e1 )
=0
6
1
3 4
2 5
e6
v +
-
e4
+ v7
KVL
+ v1
-
-
1
e1
v8 +
+
-
2
3
e3
4
datum node
+ v3
+ v10
9
6
v6 +
v2
-
+ v4
e2
-
-
5
v5 +
v1 = e6 − e5 = −e5 , v4 = e2 − e5 v2 = e1 − e5
e5
, v5 = e5 − e2
v3 = e6 − e1 = −e1 , v6 = e2 − e4
e2 1
v3
D
-
+ e3 + 3
D3
1
v4
D2
v2
-
D4
D5
e1 +
2
-
v1 +
4
-
+ v5
-
4
e4 = 0
KVL
v1 = e2 − e1 v2 = e1 − e4 = e1 v3 = e3 − e2 v4 = e3 − e4 = e3 v1 + v2 −
v4
+
v3
= (e2 − e1 ) + (e1 − e4 ) − (e3 − e4 ) + (e3 − e2 )
=0
6
1
+-
v4 3
--
v6 2
++
v5
5
4
KVL around closed node sequence 1
3
v4 − v5 + v6 = 0
2
1
:
Loop Definition A closed node sequence nm )
(na, nb, …,
is called a loop iff, there is a 2-
terminal circuit element connecting each consecutive pair of nodes (nk, nk+1), where nk is any node in the sequence.
KVL Corollary 2 (around loops)
Algebraic sum of all voltages around any loop in a connected circuit is equal to
zero at all times t.
e6
D3
1
6
datum node
+ v3
D1
-
v2
D2
4
3
e2
5
KVL around loop 5
v1 − v2 − v3 = 0
1
6
e5
2
e3
6
-
e1 +
e4
+ v1
:
e6
D3
1
6
datum node
+ v3
D1
-
v2
D2
4
-
e1 +
e4
+ v1
3
e5
2
e2
e3
5
KVL around loop formed by the 3 devices D1
D2
D3
D1 :
v1 − v2 − v3 = (e6 − e5 ) − (e1 − e5 ) − (e6 − e1 ) = 0
1
2 5
4
3
Basic Nonplanar Graph 1
1
2 5
4
3
1
2 5
4
3
It is impossible to redraw this circuit without intersecting wires. Hence, we can not define meshes in this circuit.
1
2
6
3
5
4
Basic Nonplanar Graph 2
1
2
6
3
5
4
It is impossible to redraw this circuit without intersecting wires. Hence, we can not define meshes in this circuit.
How to test for Planar G Kuratowski’s Theorem A necessary and sufficient condition for G to be a planar graph is that it does not contain either Basic Nonplanar Graph 1 or Basic Nonplanar Graph 2, as a subgraph.
Remark We can define meshes in a circuit iff its associated graph is planar
Definition: Planar Graph G
A graph G is said to be planar iff G can be redrawn on
a
plane
with
no
intersecting branches except at the nodes.
Mesh Any loop formed by branches of a circuit is called a
mesh iff the loop encloses
no other branches, or wires in its interior.
A Mesh is like a window. D1
1 D3
D4
D5
3 2
D2 D
7
D8
D6
4
There are 4 meshes in this circuit.
Every mesh is a loop, but NOT all loops are meshes!