Data Loading...
VHDL Syntax- summary (II) VHDL Syntax- summary (III) Flipbook PDF
1 EE366 – CMOS VLSI Design VHDL – Language Elements VHDL Syntax- summary • Identifiers, Numbers, Strings • variables, si
131 Views
111 Downloads
FLIP PDF 126.37KB
VHDL Syntax- summary EE366 – CMOS VLSI Design VHDL – Language Elements
VHDL Syntax- summary (II) • • • • • • •
entity declaration architecture declaration signal declaration blocks component declaration vs. instantiation Signal Assignment (assignment semantics) wait
VHDL Syntax- summary (IV) • • • • •
The Library std_logic_1164 The type Std_logic Resolved Signals, Drivers Generate VITAL
• • • • • • •
Identifiers, Numbers, Strings variables, signals, constants and types arrays, records Expressions, Operators Sequential vs. Concurrent Statements Variable Assignment If, Case, Loop, While, For, Null, Assert
VHDL Syntax- summary (III) • Concurrent vs. Sequential Signal Assignment • with .. select, when • Packages • Functions and Procedures • Design Units • Libraries, Configurations
Identifiers –reserved words • All keywords are reserved, and cannot be used to name any user-defined object (signal, variable, architecture, process, component, loop variable….) • See handout for a list of reserved words • VHDL is case insensitive!
1
Identifiers – user-defined • A valid identifier is: – Any sequence of letters, digits and isolated underline, – starting with a letter, – ending with a letter or a digit
• Ex.: valid: A a1 A_1 • non valid: _1 a_ a-b a__b • Note: VHDL’93 adds \****\ identifiers
Delimiters and separators • Separators: Space, tab, end of line. • Delimiters: – Simple: “ & # ‘ ( ) * + , - . / : ; < = > | – Compound: => = -- /= **
• Comments are introduced by -- and are valid until the end of the line
– Ex. \74ls163\ is valid in VHDL’93
Literals • Character literal :’char’ – ex.: ‘0’, ‘a’
• String literal: “string of chars”. – ex.: “a string”, “””” – Concatenation operator: & • “abc”&”def” is equivalent to “abcdef”
• Bit string literal: base_specifier“string of digits” – Ex.: “11010011”, X”E3”, O”323” – _ delimiter for readability: B”1101_0011”
Variable vs. Signal Declaration • variable varname : vartype; – Only inside processes, procedures or function – Local scope (VHDL’93 has global variables)
Numbers • They are abstract literals • Decimal integer: with or without exponent. – Ex: 34 3e5 111_111E10
• Decimal real: needs the decimal point, and a digit before and after it – Ex: 2.0e-2
• Based: uses a different base: – 4#3300#
Constants • Constant constname : type := constvalue; – Deferred constants accepted
• Ex: variable x : time :=1.0 s;
• signal signame : sigtype; – Inside architectures – Visible everywhere in the architecture • Ex: signal a,b : bit; • Ex: signal num : integer := 10;
2
Types and Strong Typing • VHDL is a strongly typed language: – Typed consistence is always checked
• Divided into 4 classes – Scalar • Discrete (enumeration and integer) • real • Physical
– Composite (arrays and records) – access (like C pointers – allow dynamic variables) – file (useful for test vectors and output dump)
Enumeration types • Simple list of values – type traffic_light is (RED, YELLOW, GREEN);
• Built-in enumeration types: – type bit is (`0`,`1`); – type boolean is (FALSE, TRUE); – type severity_level is (NOTE, WARNING, ERROR, FAILURE); – type character is (NUL, SOH,……, `A`, `B`,….,DEL);
• Practically identifiable with the numbers from 0 to n-1
Integer data types • Predefined: – type integer is range min_num to max_num; • max_num and |min_num| >= 2147483647
– subtype natural is integer range 0 to integer’high; – subtype positive is integer range 1 to integer’high;
• User-defined: – type my_int is range -10 to 200; – subtype my_pos is my_int range 0 to my_int’high;
• Subtypes can be freely used in expressions with their defining type
Real types • Predefined: – type real is range min_real_num to max_real_num; • max_real_num and |min_real_num| >= 1.0e+38
• User-defined: – type probability is range 0.0 to 1.0; – type reverse_real is range 200.0 downto -10.0;
• Subtypes can be freely used in expressions with their defining type
Physical types • Predefined: – Type time is range min_num to max_num units fs; ps = 1000 fs; ns = 1000 ps; us = 1000 ns; ms = 1000 us; sec = 1000 ms; min = 60 sec; hr = 60 min; end units;
Arrays • Like in classical programming language – type array_of_tl is array (0 to 10) of traffic_light;
• Predefined: – type string is array (positive range ) of character; – type bit_vector is array (natural range ) of bit; • Ex: signal counter : bit_vector(3 downto 0):=“0000”;
• Assignment can be made by subranges: – Counter1(3 downto 1) boolean) precedence • Adding: + - & (same base type) • Sign: + - (numeric) • Multiplicative: * / mod rem (integer and/or real) • Miscellaneous: ** abs not
Expressions • Use operators, and parentheses. • And, or are associative, nand, nor are not • VHDL ’93 has added xnor, sll, srl, sla, sra, rol, ror
Concurrent Statements • • • •
Concurrent signal assignment Concurrent assert component instantiations blocks
Sequential Statements • • • • • • • •
wait if then elsif end if; case next exit null signal assignment Sequential assert
IF…THEN…ELSIF…THEN…ENDIF • Classical if construct if condition1 then …
elsif condition2 then … elsif condition3 then … else … end if;
Arbitrary number
4
CASE…IS…WHEN … END CASE • Classical switch construct case expression is when value1 => … when value2 => … when valuen => … when others => Needed if values don’t cover all choices! … end case;
LOOP … END LOOP • Declares a loop to be executed • Without controls (while, for, exit) it executes forever [label:] loop … end loop;
FOR • Repeats the loop a number of times for loopvar in a to b loop … end loop; Ex.: for i in 0 to 100 loop sum:=sum+i end loop; • loopvar – doesn’t have to be declared – can be used inside the loop – cannot be modified in the loop
What if you don’t… • …want to do anything for some choices? • Use null statement case expression is … when others => NULL; end case;
WHILE • Exits a loop when condition fails to be true while(condition) loop … end loop;
NEXT • Skips to the end of the loop loop …; next; …; end loop; • In case of indented loop the label could be used to specify the end loop to go to by next(looplabel);
• A to/downto b can be any discrete range – Ex: for tval in traffic_light loop … end loop;
5
EXIT • Exits to the end of the loop loop …; exit; …; end loop; • In case of indented loop the label could be used to specify the end loop to go to by exit(looplabel); • Exit can have an exit condition: – exit looplabel when condition;
Inertial vs transport delays • Inertial delay (default) overwrites old events in the event list (as shown in previous lecture) – Result: glitches with delay < assignment delay are not propagated (the assignment has inertia) – Models gates
• Transport delay leaves old events in the list – Result every event scheduled is actually propagated – Models wires
• VHDL’93 adds reject to model more precisely pulse reject
with … select • Used to control assignment based on the value of an object (variable or signal): • with object select sgnl